Architecture and Organization (KA)
Computing professionals spend a considerable amount of time writing efficient code to solve a particular problem in an application domain. With the imminent ending of Moore and Dennard scaling laws, parallelism at the hardware system level has been increasing tremendously. This departure from sequential processing demands a deeper understanding of the underlying computer architecture. A computer system should not be regarded simply as a black box but rather the opposite. Programmers should take advantage of the inner computer architectural components to improve the system performance and energy efficiency through their code.
AR-Architecture and Organization KA aims at developing a deeper understanding of the hardware environment upon which all of computing is based and the interface it provides to higher software layers. The target hardware comprises the low-end embedded system processor up to the high-end datacenter multiprocessor.
The courses in this knowledge area will benefit students with a deeper understanding and appreciation of a computer system’s functional components, their characteristics, performance, and interactions, particularly the challenge of harnessing parallelism to sustain performance and energy improvements into the future. In addition, students need to understand computer architecture to develop programs that can achieve high performance and low energy consumption through a programmer’s awareness of parallelism, latency and power in homogeneous and heterogeneous processors. This KA will help Computer Science students to depart from the black box approach and become more aware of the underlying computer system.
This knowledge area has changed slightly since the CS2013 report, with changes and additions summarized as follows:
- Topics have been revised, in particular, in the Knowledge Units AR/Memory Hierarchy and AR/Performance and Energy Efficiency to accommodate recent advances in memory caching and energy consumption.
- To address emerging topics in Computer Architecture, the newly created KU AR/Heterogeneous Architectures covers at the introductory level: In-Memory Processing (PIM), Domain-Specific Architectures (e.g. Neural Network Processors), Quantum Processor – to cite a few.
- Knowledge Units have been merged given their coverage overlapping:
- AR/Multiprocessing and Alternative Architectures was merged into newly created AR/Heteregenous Architectures.
Allocation of Hours
AR. Architecture and Organization (0 Core-Tier1 hours, 16 Core-Tier2 hours)
| Core-Tier1 hours | Core-Tier2 Hours | Includes Elective | |
| AR/Digital Logic and Digital Systems | 3 | N | |
| AR/Machine-Level Data Representation | 3 | N | |
| AR/Assembly Level Machine Organization | 6 | N | |
| AR/Memory Hierarchy | 3 | N | |
| AR/Interfacing and Communication | 1 | N | |
| AR/Functional Organization | Y | ||
| AR/Performance and Energy Efficiency | Y | ||
| AR/Heterogeneous Architectures | Y |
AI/Digital Logic and Digital Systems
Topics:
- Overview and history of computer architecture
- Combinational vs. sequential logic/Field programmable gate arrays (FPGAs)
- Fundamental combinational
- Sequential logic building block
- Multiple representations/layers of interpretation (e.g. hardware is just another layer)
- Computer-aided design tools that process hardware and architectural representations
- Register transfer notation/Hardware Description Language (e.g. Verilog/VHDL/Chisel)
- Physical constraints
- Gate delays
- Fan-in and fan-out
- Energy/power
Illustrative Learning outcomes:
- Describe the progression of computer technology components from vacuum tubes to VLSI, from mainframe computer architectures to the organization of warehouse-scale computers.
- Comprehend the trend of modern computer architectures towards heterogeneity and that parallelism is inherent in all hardware systems.
- Explain the implications of the “power wall” in terms of further processor performance, power efficiency improvements and the drive towards harnessing parallelism.
- Articulate that there are many equivalent representations of computer functionality, including logical expressions and gates, and be able to use mathematical expressions to describe the functions of simple combinational and sequential circuits.
- Design the basic building blocks of a computer: arithmetic-logic unit (gate-level), registers (gate-level), central processing unit (register transfer-level), memory (register transfer-level).
- Use CAD tools for capture, synthesis, and simulation to evaluate simple building blocks (e.g., arithmetic-logic unit, registers, movement between registers) of a simple computer design.
- Assess the functional and timing diagram behavior of a simple processor implemented at the logic circuit level.
AR/Machine-Level Data Representation
Topics:
- Bits, bytes, and words
- Numeric data representation and number bases
- Fixed-point
- Floating-point system
- Signed and twos-complement representations
- Representation of non-numeric data Representation of records and arrays
Illustrative Learning outcomes:
- Explain why everything is data, including instructions, in computers.
- Explain the reasons for using different formats to represent numerical data.
- Describe how negative integers are stored in sign-magnitude and twos-complement representations.
- Explain how fixed-length number representations affect accuracy and precision.
- Describe the internal representation of non-numeric data, such as characters, strings, records, and arrays.
- Convert numerical data from one format to another.
AR/Assembly Level Machine Organization
Topics:
- John von Neumann machine architecture
- Control unit; instruction fetch, decode, and execution
- Instruction Set Architecture (ISA) (e.g. x86, ARM and RISC-V)
- Instruction formats
- Data manipulation, control, I/O
- Addressing modes
- Assembly/machine language programming
- Subroutine call and return mechanisms (xref PL/Language Translation and Execution)
- I/O and interrupts
- Segmentation: Heap, Static, Stack and Code segments
- Shared memory multiprocessors/multicore organization
- Introduction to SIMD vs. MIMD and the Flynn Taxonomy
Illustrative Learning outcomes:
- Explain the organization of the classical von Neumann machine and its central functional units.
- Describe how instruction is executed in a classical von Neumann machine, with extensions for threads, multiprocessor synchronization, and SIMD execution.
- Describe instruction-level parallelism and hazards, and how they are managed in typical processor pipelines.
- Summarize how instructions are represented at both the machine level and in the context of a symbolic assembler.
- Demonstrate how to map between high-level language patterns into assembly/machine language notations.
- Explain different instruction formats, such as addresses per instruction and variable-length vs. fixed-length formats.
- Explain how subroutine calls are handled at the assembly level.
- Explain the basic concepts of interrupts and I/O operations. (intersection with the OS KA)
- Write simple assembly language program segments(e.g. string processing and manipulation).
AR/Memory Hierarchy
Topics:
- Memory hierarchy: the importance of temporal and spatial locality
- Main memory organization and operations
- Persistent memory (e.g. SSD, standard disks)
- Latency, cycle time, bandwidth, and interleaving
- Cache memories
- Address mapping
- Block size
- Replacement and store policy
- Multiprocessor cache consistency
- Memory system for inter-core synchronization
- Atomic memory operations in multiprocessor system
- Virtual memory (hardware support, cross-reference OS/Virtual Memory)
- Fault handling and reliability
- Reliability (cross-reference SF/Reliability through Redundancy)
- Error coding
- Data compression
- Data integrity
- (cross-reference SF/Reliability through Redundancy)
Illustrative Learning outcomes:
- Identify the main types of memory technology (e.g., SRAM, DRAM) and their relative cost and performance.
- Explain the effect of memory latency on running time.
- Describe how the use of memory hierarchy (cache, virtual memory) is used to reduce the effective memory latency.
- Describe the principles of memory management.
- Explain the workings of a system with virtual memory management.
- Compute Average Memory Access Time under a variety of cache and memory configurations and mixes of instruction and data references.
AR/Interfacing and Communication
Topics:
- I/O fundamentals
- Handshaking and buffering
- Programmed I/O
- Interrupt-driven I/O
- Interrupt structures: vectored and prioritized, interrupt acknowledgement
- External storage, physical organization, and drives
- Buses fundamentals
- Bus protocols
- Arbitration
- Direct-memory access (DMA)
- Introduction to communication networks (cross-reference with Network KA
Illustrative Learning outcomes:
- Explain how interrupts are used to implement I/O control and data transfers.
- Identify various types of buses in a computer system.
- Describe data access from a magnetic disk drive.
- Compare common network organizations, such as ethernet/bus, ring, switched vs. routed.
AR/Functional Organization
Topics:
- Implementation of simple datapaths, including instruction pipelining, hazard detection and resolution
- Control unit
- Hardwired implementation
- Microprogrammed realization
- Instruction pipelining
- Introduction to instruction-level parallelism (ILP)
Illustrative Learning outcomes:
- Compare alternative implementation of datapaths.
- Discuss the generation of control signals using hardwired or microprogrammed implementations.
- Explain basic instruction-level parallelism using pipelining and the major hazards that may occur.
- Design and implement a complete processor, including datapath and control.
- Calculate the average cycles per instruction for a given processor and memory system implementation.
AR/Heterogeneous Architectures
Topics:
- SIMD and MIMD instruction sets and architectures (e.g. General-Purpose GPUs, TPUs/NPUs)
- Distributed heterogeneous memory system
- Shared multiprocessor memory
- Multiprocessor cache coherence
- Domain-Specific Architectures (DSAs)
- Machine Learning Accelerator
- In-networking computing
- Embedded systems for emerging applications (e.g. IoT, virtual/augmented reality, robotics)
- Neuromorphic computing
- Non-von Neumann Architectures
- In-Memory Processing (PIM)
- Neuromorphic Computing
- Matrix computing for artificial neural networks and spiking neural networks applications
- Quantum Processor
- Concepts and principles
- Data versus control paths
Illustrative Learning outcomes:
- Discuss the concept of parallel processing beyond the classical von Neumann model.
- Describe alternative parallel architectures such as SIMD and MIMD.
- Discuss the unique concerns that multiprocessing systems present concerning memory management and describe how these are addressed.
- Describe the differences between memory backplane, processor memory interconnect, and remote memory via networks, their implications for access latency and their impact on program performance.
- Discuss the underlying concept of a domain-specific accelerator in contrast with a general-purpose CPU.
- Compare the architectural design principles between a vector and scalar based processing unit.
- Explain the design principles of a quantum processor.
Desirable Professional Dispositions
The most desirable professional dispositions for this knowledge area are:
- Self-directed: self-learner, self-motivated to acquire complementary knowledge from technical documentation.
- Pro-active: students should appreciate that a computer system is a layered architecture that brings together programming, parallel and distributed computing and computer architecture. Students need to be pro-active and independent to navigate and learn from different knowledge areas.
- Inventive: look beyond simple solutions in computer architecture design issues.
- Professional: computer systems, particularly embedded sensors, can directly interface with the user’s body (e.g. real-time glucose monitoring). Students should exercise discretion, behave ethically and appreciate user safety, security and privacy concerns.
Necessary and Desirable Math
The Math necessary for this knowledge area includes:
- Discrete Math:
- Sets, Relations, Logical Operations, Number Theory
- Linear Algebra:
- Arithmetic Operations, Matrix operations
The Math desirable for this knowledge includes:
- Differential and integral calculus
- Physics for Quantum Computing
- Probability and Factorial Experimental Design for System Performance Evaluation
Shared and Crosscutting Concepts
This knowledge area shares the following concepts with other knowledge areas:
- Virtual memory (AR/Memory Hierarchy) with OS/Memory Management.
- Error coding, data compression, and data integrity (AR/Memory Hierarchy) with (SF/Software Reliability)
- Communications networks (AR/Interfacing and Communication) with (NC/Introduction)
- Processor architecture design (AR/Heteregenous Architectures with Platform-based Development (PBD/Mobile and PBD/Industrial)
- Domain-specific architectures (AR/Heteregenous Architectures) with Intelligent Systems (IS/Advanced Machine Learning)
- Emerging hardware user interfaces (AR/Heterogeneous Architectures) with Human-Computer Interaction (HCI/Human Factors & Security)
- Underlying parallel computer system (AR/Assembly Level Machine Organization) with Parallel and Distributed Computing (PD/Parallel Architecture)
Crosscutting concepts that apply to this knowledge area include:
- Parallelism at different levels
- Resource allocation, scheduling and isolation
- Performance and Energy Efficiency
- Social and environmental impacts of underlying computer systems
Subcommittee
Chair: Marcelo Pias, Federal University of Rio Grande (FURG), Brazil
Subcommittee members:
- Brett A. Becker, University College Dublin, Ireland
- Mohamed Zahran, New York University, NY
- Monica D. Anderson, University of Alabama, Tuscaloosa, AL
- Qiao Xiang, Xiamen University, China